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<title>Program counter</title>

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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Program counter</span></span>

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<p>The <b>program counter</b> (<b>PC</b>),<sup id="cite_ref-CompArchOrg_1-0" class="reference"><a href="#cite_note-CompArchOrg-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> commonly called the <b>instruction pointer</b> (<b>IP</b>) in <a href="Intel" title="Intel">Intel</a> <a href="X86" title="X86">x86</a> and <a href="Itanium" title="Itanium">Itanium</a> <a href="Microprocessor" title="Microprocessor">microprocessors</a>, and sometimes called the <b>instruction address register</b> (<b>IAR</b>),<sup id="cite_ref-Mead_1980_2-0" class="reference"><a href="#cite_note-Mead_1980-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-CompArchOrg_1-1" class="reference"><a href="#cite_note-CompArchOrg-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> the <b>instruction counter</b>,<sup id="cite_ref-IBM_1953_3-0" class="reference"><a href="#cite_note-IBM_1953-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> or just part of the instruction sequencer,<sup id="cite_ref-Katzan_1971_4-0" class="reference"><a href="#cite_note-Katzan_1971-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> is a <a href="Processor_register" title="Processor register">processor register</a> that indicates where a <a href="Computer" title="Computer">computer</a> is in its <a href="Computer_program" title="Computer program">program</a> sequence.<sup id="cite_ref-a238_5-0" class="reference"><a href="#cite_note-a238-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-NB1_6-0" class="reference"><a href="#cite_note-NB1-6"><span class="cite-bracket">[</span>nb 1<span class="cite-bracket">]</span></a></sup>

</p><p>Usually, the PC is incremented after fetching an <a href="Instruction_(computer_science)" class="mw-redirect" title="Instruction (computer science)">instruction</a>, and holds the <a href="Memory_address" title="Memory address">memory address</a> of ("<a href="Pointer_(computer_programming)" title="Pointer (computer programming)">points</a> to") the next instruction that would be executed.<sup id="cite_ref-Silberschatz_2018_7-0" class="reference"><a href="#cite_note-Silberschatz_2018-7"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-NB2_9-0" class="reference"><a href="#cite_note-NB2-9"><span class="cite-bracket">[</span>nb 2<span class="cite-bracket">]</span></a></sup>

</p><p>Processors usually fetch instructions sequentially from <a href="Computer_memory" title="Computer memory">memory</a>, but <i>control transfer</i> instructions change the sequence by placing a new value in the PC. These include <a href="Branch_(computer_science)" title="Branch (computer science)">branches</a> (sometimes called jumps), <a href="Subroutine" class="mw-redirect" title="Subroutine">subroutine</a> calls, and <a href="Return_statement" title="Return statement">returns</a>. A transfer that is conditional on the truth of some assertion lets the computer follow a different sequence under different conditions.

</p><p>A branch provides that the next instruction is fetched from elsewhere in memory. A subroutine call not only branches but saves the preceding contents of the PC somewhere. A return retrieves the saved contents of the PC and places it back in the PC, resuming sequential execution with the instruction following the subroutine call.

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<div class="mw-heading mw-heading2"><h2 id="Hardware_implementation">Hardware implementation</h2></div>

<p>In a simple <a href="Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU), the PC is a <a href="Counter_(digital)" title="Counter (digital)">digital counter</a> (which is the origin of the term "program counter") that may be one of several hardware <a href="Processor_register" title="Processor register">registers</a>. The <a href="Instruction_cycle" title="Instruction cycle">instruction cycle</a><sup id="cite_ref-Hennessy_1990_10-0" class="reference"><a href="#cite_note-Hennessy_1990-10"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> begins with a <i>fetch</i>, in which the CPU places the value of the PC on the <a href="Address_bus" class="mw-redirect" title="Address bus">address bus</a> to send it to the memory. The memory responds by sending the contents of that memory location on the <a href="Memory_bus" class="mw-redirect" title="Memory bus">data bus</a>. (This is the <a href="Stored-program_computer" title="Stored-program computer">stored-program computer</a> model, in which a single memory space contains both executable instructions and ordinary data.<sup id="cite_ref-Randall_1982_11-0" class="reference"><a href="#cite_note-Randall_1982-11"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup>) Following the fetch, the CPU proceeds to <i>execution</i>, taking some action based on the memory contents that it obtained. At some point in this cycle, the PC will be modified so that the next instruction executed is a different one (typically, incremented so that the next instruction is the one starting at the memory address immediately following the last memory location of the current instruction).

</p><p>Like other processor registers, the PC may be a bank of binary latches, each one representing one bit of the value of the PC.<sup id="cite_ref-Bell_1971_12-0" class="reference"><a href="#cite_note-Bell_1971-12"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> The number of bits (the width of the PC) relates to the processor architecture. For instance, a “32-bit” CPU may use 32 bits to be able to address 2<sup>32</sup> units of memory. On some processors, the width of the program counter instead depends on the addressable memory; for example, some <a href="AVR_microcontrollers" title="AVR microcontrollers">AVR microcontrollers</a> have a PC which wraps around after 12 bits.<sup id="cite_ref-Arnold_2020_AS_13-0" class="reference"><a href="#cite_note-Arnold_2020_AS-13"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup>

</p><p>If the PC is a binary counter, it may increment when a pulse is applied to its COUNT UP input, or the CPU may compute some other value and load it into the PC by a pulse to its LOAD input.<sup id="cite_ref-Walker_1967_14-0" class="reference"><a href="#cite_note-Walker_1967-14"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup>

</p><p>To identify the current instruction, the PC may be combined with other registers that identify a <a href="Segmentation_(memory)" class="mw-redirect" title="Segmentation (memory)">segment</a> or <a href="Page_(computer_memory)" title="Page (computer memory)">page</a>. This approach permits a PC with fewer bits by assuming that most memory units of interest are within the current vicinity.

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<div class="mw-heading mw-heading2"><h2 id="Consequences_in_machine_architecture">Consequences in machine architecture</h2></div>

<p>Use of a PC that normally increments assumes that what a computer does is execute a usually linear sequence of instructions. Such a PC is central to the <a href="Von_Neumann_architecture" title="Von Neumann architecture">von Neumann architecture</a>. Thus programmers write a sequential <a href="Control_flow" title="Control flow">control flow</a> even for algorithms that do not have to be sequential. The resulting “<a href="Von_Neumann_bottleneck" class="mw-redirect" title="Von Neumann bottleneck">von Neumann bottleneck</a>” led to research into <a href="Parallel_computing" title="Parallel computing">parallel computing</a>,<sup id="cite_ref-Chambers_1984_15-0" class="reference"><a href="#cite_note-Chambers_1984-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> including non-von Neumann or <a href="Dataflow" title="Dataflow">dataflow</a> models that did not use a PC; for example, rather than specifying sequential steps, the high-level programmer might specify desired <a href="Functional_programming" title="Functional programming">function</a> and the low-level programmer might specify this using <a href="Combinatory_logic" title="Combinatory logic">combinatory logic</a>.

</p><p>This research also led to ways to making conventional, PC-based, CPUs run faster, including:

</p>

<ul><li><a href="Pipeline_(computing)" title="Pipeline (computing)">Pipelining</a>, in which different hardware in the CPU executes different phases of multiple instructions simultaneously.</li>

<li>The <a href="Very_long_instruction_word" title="Very long instruction word">very long instruction word</a> (VLIW) architecture, where a single instruction can achieve multiple effects.</li>

<li>Techniques to predict <a href="Out-of-order_execution" title="Out-of-order execution">out-of-order execution</a> and prepare subsequent instructions for execution outside the regular sequence.</li></ul>

<div class="mw-heading mw-heading2"><h2 id="Consequences_in_high-level_programming">Consequences in high-level programming</h2></div>

<p>Modern high-level <a href="Programming_language" title="Programming language">programming languages</a> still follow the sequential-execution model and, indeed, a common way of identifying programming errors is with a “procedure execution” in which the programmer's finger identifies the point of execution as a PC would. The high-level language is essentially the machine language of a virtual machine,<sup id="cite_ref-Hofstadter_1980_16-0" class="reference"><a href="#cite_note-Hofstadter_1980-16"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> too complex to be built as hardware but instead emulated or <a href="Interpreter_(computing)" title="Interpreter (computing)">interpreted</a> by software.

</p><p>However, new programming models transcend sequential-execution programming:

</p>

<ul><li>When writing a <a href="Thread_(computing)" title="Thread (computing)">multi-threaded</a> program, the programmer may write each thread as a sequence of instructions without specifying the timing of any instruction relative to instructions in other threads.</li>

<li>In <a href="Event-driven_programming" title="Event-driven programming">event-driven programming</a>, the programmer may write sequences of instructions to respond to <a href="Event_(computing)" title="Event (computing)">events</a> without specifying an overall sequence for the program.</li>

<li>In <a href="Dataflow_programming" title="Dataflow programming">dataflow programming</a>, the programmer may write each section of a computing <a href="Pipeline_programming" class="mw-redirect" title="Pipeline programming">pipeline</a> without specifying the timing relative to other sections.</li></ul>

<ul><li><a href="Branch_prediction" class="mw-redirect" title="Branch prediction">Branch prediction</a></li>

<li><a href="Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li>

<li><a href="Instruction_cycle" title="Instruction cycle">Instruction cycle</a></li>

<li><a href="Instruction_unit" title="Instruction unit">Instruction unit</a></li>

<li><a href="Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">Instruction pipeline</a></li>

<li><a href="Instruction_register" title="Instruction register">Instruction register</a></li>

<li><a href="Instruction_scheduling" title="Instruction scheduling">Instruction scheduling</a></li>

<li><a href="Program_status_word" title="Program status word">Program status word</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2></div>

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<li id="cite_note-NB1-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-NB1_6-0">^</a></b></span> <span class="reference-text">For modern processors, the concept of "where it is in its sequence" is too simplistic, as <a href="Instruction-level_parallelism" title="Instruction-level parallelism">instruction-level parallelism</a> and <a href="Out-of-order_execution" title="Out-of-order execution">out-of-order execution</a> may occur.</span>

</li>

<li id="cite_note-NB2-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-NB2_9-0">^</a></b></span> <span class="reference-text">In a processor where the incrementation precedes the fetch, the PC points to the current instruction being executed. In some processors, the PC points some distance beyond the current instruction; for instance, in the <a href="ARM7" title="ARM7">ARM7</a>, the value of PC visible to the programmer points beyond the current instruction and beyond the <a href="Delay_slot" title="Delay slot">delay slot</a>.<sup id="cite_ref-ARM_AG12_8-0" class="reference"><a href="#cite_note-ARM_AG12-8"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup></span>

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<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite id="CITEREFHayes1978" class="citation book cs1">Hayes, John P. (1978). <i>Computer Architecture and Organization</i>. McGraw-Hill. p. 245. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-07-027363-4</bdi>.</cite></span>

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<li id="cite_note-Mead_1980-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-Mead_1980_2-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFMeadConway1980" class="citation book cs1"><a href="Carver_Mead" title="Carver Mead">Mead, Carver</a>; <a href="Lynn_Conway" title="Lynn Conway">Conway, Lynn</a> (1980). <span class="id-lock-registration" title="Free registration required"><a rel="nofollow" class="external text" href="https://archive.org/details/introductiontovl00mead"><i>Introduction to VLSI Systems</i></a></span>. Reading, USA: <a href="Addison-Wesley" title="Addison-Wesley">Addison-Wesley</a>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-201-04358-0</bdi>.</cite></span>

</li>

<li id="cite_note-IBM_1953-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-IBM_1953_3-0">^</a></b></span> <span class="reference-text"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="http://bitsavers.org/pdf/ibm/701/24-6042-1_701_PrincOps.pdf"><i>Principles of Operation, Type 701 and Associated Equipment</i></a> <span class="cs1-format">(PDF)</span>. <a href="IBM" title="IBM">IBM</a>. 1953.</cite></span>

</li>

<li id="cite_note-Katzan_1971-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-Katzan_1971_4-0">^</a></b></span> <span class="reference-text">Harry Katzan (1971), <i>Computer Organization and the System/370</i>, <a href="Van_Nostrand_Reinhold_Company" class="mw-redirect" title="Van Nostrand Reinhold Company">Van Nostrand Reinhold Company</a>, New York, USA, LCCCN 72-153191</span>

</li>

<li id="cite_note-a238-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-a238_5-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFBates2011" class="citation book cs1">Bates, Martin (2011). "Microcontroller Operation". <i>PIC Microcontrollers</i>. Elsevier. pp. <span class="nowrap">27–</span>44. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1016%2Fb978-0-08-096911-4.10002-3">10.1016/b978-0-08-096911-4.10002-3</a>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-0-08-096911-4</bdi>. <q>Program Counter (PC) is a register that keeps track of the program sequence, by storing the address of the instruction currently being executed. It is automatically loaded with zero when the chip is powered up or reset. As each instruction is executed, PC is incremented (increased by one) to point to the next instruction.</q></cite></span>

</li>

<li id="cite_note-Silberschatz_2018-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-Silberschatz_2018_7-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFSilberschatzGagneGalvin2018" class="citation book cs1"><a href="Abraham_Silberschatz" title="Abraham Silberschatz">Silberschatz, Abraham</a>; Gagne, Greg; Galvin, Peter B. (April 2018). <a rel="nofollow" class="external text" href="https://www.wiley.com/en-us/Operating+System+Concepts%2C+10th+Edition-p-9781119320913"><i>Operating System Concepts</i></a>. United States: <a href="Wiley_(publisher)" title="Wiley (publisher)">Wiley</a>. pp. 27, G-29. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-1-119-32091-3</bdi>.</cite></span>

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<li id="cite_note-ARM_AG12-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-ARM_AG12_8-0">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/Bcfihdhj.html#id2766362">"ARM Developer Suite, Assembler Guide. Version 1.2"</a>. <a href="ARM_Limited" class="mw-redirect" title="ARM Limited">ARM Limited</a>. 2001<span class="reference-accessdate">. Retrieved <span class="nowrap">2019-10-18</span></span>.</cite></span>

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<li id="cite_note-Hennessy_1990-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-Hennessy_1990_10-0">^</a></b></span> <span class="reference-text"><a href="John_L._Hennessy" title="John L. Hennessy">John L. Hennessy</a> and <a href="David_Patterson_(scientist)" class="mw-redirect" title="David Patterson (scientist)">David A. Patterson</a> (1990), <i>Computer Architecture: a quantitative approach</i>, <a href="Morgan_Kaufmann_Publishers" title="Morgan Kaufmann Publishers">Morgan Kaufmann Publishers</a>, Palo Alto, USA, <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>1-55860-069-8</bdi></span>

</li>

<li id="cite_note-Randall_1982-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-Randall_1982_11-0">^</a></b></span> <span class="reference-text">B. Randall (1982), <i>The Origins of Digital Computers</i>, <a href="Springer-Verlag" class="mw-redirect" title="Springer-Verlag">Springer-Verlag</a>, Berlin, D</span>

</li>

<li id="cite_note-Bell_1971-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-Bell_1971_12-0">^</a></b></span> <span class="reference-text"><a href="C._Gordon_Bell" class="mw-redirect" title="C. Gordon Bell">C. Gordon Bell</a> and <a href="Allen_Newell" title="Allen Newell">Allen Newell</a> (1971), <i>Computer Structures: Readings and Examples</i>, <a href="McGraw-Hill_Book_Company" class="mw-redirect" title="McGraw-Hill Book Company">McGraw-Hill Book Company</a>, New York, USA</span>

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<li id="cite_note-Arnold_2020_AS-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-Arnold_2020_AS_13-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFArnold2020" class="citation book cs1">Arnold, Alfred (2020) [1996, 1989]. <a rel="nofollow" class="external text" href="http://john.ccac.rwth-aachen.de:8000/as/as_EN.html#sect_E_">"E. Predefined Symbols"</a>. <a rel="nofollow" class="external text" href="http://john.ccac.rwth-aachen.de:8000/as/as_EN.html"><i>Macro Assembler AS – User's Manual</i></a>. V1.42. Translated by Arnold, Alfred; Hilse, Stefan; Kanthak, Stephan; Sellke, Oliver; De Tomasi, Vittorio. p. Table E.3: Predefined Symbols – Part 3. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200228144943/http://john.ccac.rwth-aachen.de:8000/as/as_EN.html">Archived</a> from the original on 2020-02-28<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-02-28</span></span>. <q>3.2.12. WRAPMODE […] AS will assume that the processor's program counter does not have the full length of 16 bits given by the architecture, but instead a length that is exactly sufficient to address the internal ROM. For example, in case of the <a href="AT90S8515" class="mw-redirect" title="AT90S8515">AT90S8515</a>, this means 12 bits, corresponding to 4 Kwords or 8 Kbytes. This assumption allows relative branches from the ROM's beginning to the end and vice versa which would result in an out-of-branch error when using strict arithmetics. Here, they work because the carry bits resulting from the target address computation are discarded. […] In case of the abovementioned AT90S8515, this option is even necessary because it is the only way to perform a direct jump through the complete address space […]</q></cite></span>

</li>

<li id="cite_note-Walker_1967-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-Walker_1967_14-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFWalker1967" class="citation book cs1">Walker, B. S. (1967). <i>Introduction to Computer Engineering</i>. London, UK: <a href="University_of_London_Press" title="University of London Press">University of London Press</a>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-340-06831-0</bdi>.</cite></span>

</li>

<li id="cite_note-Chambers_1984-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-Chambers_1984_15-0">^</a></b></span> <span class="reference-text">F. B. Chambers, D. A. Duce and G. P. Jones (1984), <i>Distributed Computing</i>, <a href="Academic_Press" title="Academic Press">Academic Press</a>, Orlando, USA, <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-12-167350-2</bdi></span>

</li>

<li id="cite_note-Hofstadter_1980-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-Hofstadter_1980_16-0">^</a></b></span> <span class="reference-text"><a href="Douglas_Hofstadter" title="Douglas Hofstadter">Douglas Hofstadter</a> (1980), <i>Gödel, Escher, Bach: an eternal golden braid</i>, <a href="Penguin_Books" title="Penguin Books">Penguin Books</a>, Harmondsworth, UK, <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-14-005579-7</bdi></span>

</li>

</ol></div></div>

/* start https://en.wikipedia.org/ */

.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist li::after{content:" · ";font-weight:bold}.mw-parser-output .hlist dd:last-child::after,.mw-parser-output .hlist dt:last-child::after,.mw-parser-output .hlist li:last-child::after{content:none}.mw-parser-output .hlist dd dd:first-child::before,.mw-parser-output .hlist dd dt:first-child::before,.mw-parser-output .hlist dd li:first-child::before,.mw-parser-output .hlist dt dd:first-child::before,.mw-parser-output .hlist dt dt:first-child::before,.mw-parser-output .hlist dt li:first-child::before,.mw-parser-output .hlist li dd:first-child::before,.mw-parser-output .hlist li dt:first-child::before,.mw-parser-output .hlist li li:first-child::before{content:" (";font-weight:normal}.mw-parser-output .hlist dd dd:last-child::after,.mw-parser-output .hlist dd dt:last-child::after,.mw-parser-output .hlist dd li:last-child::after,.mw-parser-output .hlist dt dd:last-child::after,.mw-parser-output .hlist dt dt:last-child::after,.mw-parser-output .hlist dt li:last-child::after,.mw-parser-output .hlist li dd:last-child::after,.mw-parser-output .hlist li dt:last-child::after,.mw-parser-output .hlist li li:last-child::after{content:")";font-weight:normal}.mw-parser-output .hlist ol{counter-reset:listitem}.mw-parser-output .hlist ol>li{counter-increment:listitem}.mw-parser-output .hlist ol>li::before{content:" "counter(listitem)"\a0 "}.mw-parser-output .hlist dd ol>li:first-child::before,.mw-parser-output .hlist dt ol>li:first-child::before,.mw-parser-output .hlist li ol>li:first-child::before{content:" ("counter(listitem)"\a0 "}

/* end https://en.wikipedia.org/ */

</style><style data-mw-deduplicate="TemplateStyles:r1236075235">

/* start https://en.wikipedia.org/ */

.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output .navbox+.navbox-styles+.navbox{margin-top:-1px}.mw-parser-output .navbox-inner,.mw-parser-output .navbox-subgroup{width:100%}.mw-parser-output .navbox-group,.mw-parser-output .navbox-title,.mw-parser-output .navbox-abovebelow{padding:0.25em 1em;line-height:1.5em;text-align:center}.mw-parser-output .navbox-group{white-space:nowrap;text-align:right}.mw-parser-output .navbox,.mw-parser-output .navbox-subgroup{background-color:#fdfdfd}.mw-parser-output .navbox-list{line-height:1.5em;border-color:#fdfdfd}.mw-parser-output .navbox-list-with-group{text-align:left;border-left-width:2px;border-left-style:solid}.mw-parser-output tr+tr>.navbox-abovebelow,.mw-parser-output tr+tr>.navbox-group,.mw-parser-output tr+tr>.navbox-image,.mw-parser-output tr+tr>.navbox-list{border-top:2px solid #fdfdfd}.mw-parser-output .navbox-title{background-color:#ccf}.mw-parser-output .navbox-abovebelow,.mw-parser-output .navbox-group,.mw-parser-output .navbox-subgroup .navbox-title{background-color:#ddf}.mw-parser-output .navbox-subgroup .navbox-group,.mw-parser-output .navbox-subgroup .navbox-abovebelow{background-color:#e6e6ff}.mw-parser-output .navbox-even{background-color:#f7f7f7}.mw-parser-output .navbox-odd{background-color:transparent}.mw-parser-output .navbox .hlist td dl,.mw-parser-output .navbox .hlist td ol,.mw-parser-output .navbox .hlist td ul,.mw-parser-output .navbox td.hlist dl,.mw-parser-output .navbox td.hlist ol,.mw-parser-output .navbox td.hlist ul{padding:0.125em 0}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}

/* end https://en.wikipedia.org/ */

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.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}

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</style><div id="x86_assembly_topics102" style="font-size:114%;margin:0 4em">x86 assembly topics</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Topics</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Assembly_language" title="Assembly language">Assembly language</a></li>

<li><a href="Comparison_of_assemblers" title="Comparison of assemblers">Comparison of assemblers</a></li>

<li><a href="Disassembler" title="Disassembler">Disassembler</a></li>

<li><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></li>

<li><a href="Low-level_programming_language" title="Low-level programming language">Low-level programming language</a></li>

<li><a href="Machine_code" title="Machine code">Machine code</a></li>

<li><a href="Microassembler" title="Microassembler">Microassembler</a></li>

<li><a href="X86_assembly_language" title="X86 assembly language">x86 assembly language</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Comparison_of_assemblers#x86_assemblers" title="Comparison of assemblers">Assemblers</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="FASM" title="FASM">Flat Assembler</a> (FASM)</li>

<li><a href="GNU_Assembler" title="GNU Assembler">GNU Assembler</a> (GAS)</li>

<li><a href="High_Level_Assembly" title="High Level Assembly">High Level Assembly</a> (HLA)</li>

<li><a href="Microsoft_Macro_Assembler" title="Microsoft Macro Assembler">Microsoft Macro Assembler</a> (MASM)</li>

<li><a href="Netwide_Assembler" title="Netwide Assembler">Netwide Assembler</a> (NASM)</li>

<li><a href="Turbo_Assembler" title="Turbo Assembler">Turbo Assembler</a> (TASM)</li>

<li><a href="Open_Watcom_Assembler" title="Open Watcom Assembler">Open Watcom Assembler</a> (WASM)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Programming<br>issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Call_stack" title="Call stack">Call stack</a></li>

<li><a href="FLAGS_register" title="FLAGS register">Flags</a>

<ul><li><a href="Carry_flag" title="Carry flag">Carry flag</a></li>

<li><a href="Direction_flag" title="Direction flag">Direction flag</a></li>

<li><a href="Interrupt_flag" title="Interrupt flag">Interrupt flag</a></li>

<li><a href="Overflow_flag" title="Overflow flag">Overflow flag</a></li>

<li><a href="Memory_address" title="Memory address">Memory address</a></li>

<li><a href="Opcode" title="Opcode">Opcode</a></li>

<li><a href="Processor_register" title="Processor register">Processor register</a></li>

<li><a href="X86_calling_conventions" title="X86 calling conventions">Calling conventions</a></li>

<li><a href="X86_instruction_listings" title="X86 instruction listings">Instruction listings</a></li>

<li><a href="X86#x86_registers" title="X86">Registers</a></li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Processor_technologies439" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Processor_technologies439" style="font-size:114%;margin:0 4em"><a href="Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Abstract_machine" title="Abstract machine">Abstract machine</a></li>

<li><a href="Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li>

<li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li>

<li><a href="Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li>

<li><a href="Queue_automaton" title="Queue automaton">Queue automaton</a></li>

<li><a href="Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li>

<li><a href="Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li>

<li><a href="Turing_machine" title="Turing machine">Turing machine</a>

<ul><li><a href="Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li>

<li><a href="Universal_Turing_machine" title="Universal Turing machine">Universal</a></li>

<li><a href="Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li>

<li><a href="Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li>

<li><a href="Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li>

<li><a href="Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li>

<li><a href="Hypercomputation" title="Hypercomputation">Hypercomputation</a></li>

<li><a href="Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li>

<li><a href="History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li>

<li><a href="Stack_machine" title="Stack machine">Stack machine</a></li>

<li><a href="Register_machine" title="Register machine">Register machines</a>

<ul><li><a href="Counter_machine" title="Counter machine">Counter</a></li>

<li><a href="Pointer_machine" title="Pointer machine">Pointer</a></li>

<li><a href="Random-access_machine" title="Random-access machine">Random-access</a></li>

<li><a href="Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></li>

<li><a href="Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li>

<li><a href="Harvard_architecture" title="Harvard architecture">Harvard</a>

<ul><li><a href="Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li>

<li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>

<li><a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li>

<li><a href="Cellular_architecture" title="Cellular architecture">Cellular</a></li>

<li><a href="Endianness" title="Endianness">Endianness</a></li>

<li><a href="Computer_data_storage" title="Computer data storage">Memory access</a>

<li><a href="Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li>

<li><a href="Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li>

<li><a href="Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li>

<li><a href="Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a>

<ul><li><a href="Virtual_memory" title="Virtual memory">Virtual memory</a></li>

<li><a href="Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li>

<li><a href="Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li>

<li><a href="Fabric_computing" title="Fabric computing">Fabric</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Cognitive_computing" title="Cognitive computing">Cognitive</a></li>

<li><a href="Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set<br>architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li>

<li><a href="Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li>

<ul><li><a href="TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Quantum_computing" title="Quantum computing">Quantum computing</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a>

<ul><li><a href="Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br>sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li>

<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li>

<li>Power

<ul><li><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li>

<li><a href="PowerPC" title="PowerPC">PowerPC</a></li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li></ul></li>

<li><a href="Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li>

<li><a href="SPARC" title="SPARC">SPARC</a></li>

<li><a href="SuperH" title="SuperH">SuperH</a></li>

<li><a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li>

<li><a href="ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li>

<li><a href="Unicore" title="Unicore">Unicore</a></li>

<li><a href="IA-64" title="IA-64">Itanium</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li>System/3x0

<li><a href="Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li>

<li>Tilera ISA</li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Adapteva" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li>

<li><a href="Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li>

<li><a href="Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Data_dependency" title="Data dependency">Data dependency</a></li>

<li><a href="Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li>

<li><a href="Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li>

<li><a href="False_sharing" title="False sharing">False sharing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Scoreboarding" title="Scoreboarding">Scoreboarding</a></li>

<li><a href="Tomasulo's_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a>

<ul><li><a href="Reservation_station" title="Reservation station">Reservation station</a></li>

<li><a href="Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li>

<li><a href="Register_renaming" title="Register renaming">Register renaming</a></li>

<li><a href="Wide-issue" title="Wide-issue">Wide-issue</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Branch_predictor" title="Branch predictor">Branch prediction</a></li>

<li><a href="Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li>

<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>

<li><a href="Instruction_pipelining" title="Instruction pipelining">Pipelining</a>

<ul><li><a href="Scalar_processor" title="Scalar processor">Scalar</a></li>

<li><a href="Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li>

<ul><li><a href="Thread_(computing)" title="Thread (computing)">Thread</a></li>

<li><a href="Process_(computing)" title="Process (computing)">Process</a></li></ul></li>

<ul><li><a href="Vector_processor" title="Vector processor">Vector</a></li></ul></li>

<li><a href="Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>

<li><a href="Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>

<li><a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a>

<ul><li><a href="Hyper-threading" title="Hyper-threading">Hyperthreading</a></li>

<li><a href="Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li>

<li><a href="Speculative_multithreading" title="Speculative multithreading">Speculative</a></li>

<li><a href="Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>

<li><a href="Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li>

<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li>

<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_performance" title="Computer performance">Processor<br>performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor_count" title="Transistor count">Transistor count</a></li>

<li><a href="Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC)

<ul><li><a href="Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li>

<li><a href="Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li>

<li><a href="FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li>

<li><a href="Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li>

<li><a href="SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li>

<li><a href="Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li>

<li><a href="Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)

<ul><li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li>

<li><a href="Vector_processor" title="Vector processor">Vector</a></li>

<li><a href="Barrel_processor" title="Barrel processor">Barrel</a></li>

<li><a href="Stream_processing" title="Stream processing">Stream</a></li>

<li><a href="Tile_processor" title="Tile processor">Tile processor</a></li>

<li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li>

<li><a href="System_in_a_package" title="System in a package">System in a package</a> (SiP)</li>

<li><a href="Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Embedded_system" title="Embedded system">Embedded system</a></li>

<li><a href="Microprocessor" title="Microprocessor">Microprocessor</a></li>

<li><a href="Microcontroller" title="Microcontroller">Microcontroller</a></li>

<li><a href="Mobile_processor" title="Mobile processor">Mobile</a></li>

<li><a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br>on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li>

<li><a href="Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li>

<li><a href="Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li>

<li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_acceleration" title="Hardware acceleration">Hardware<br>accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerator</a></li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li>

<li><a href="Image_processor" title="Image processor">Image processor</a></li>

<li><a href="Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li>

<li><a href="Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li>

<li><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li>

<li><a href="Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li>

<li><a href="Network_processor" title="Network processor">Network processor</a></li>

<li><a href="Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Bit_slicing" title="Bit slicing">bit slicing</a></li>

<li><a href="Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a>

<ul><li><a href="Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single-core" title="Single-core">Single-core</a></li>

<li><a href="Multi-core_processor" title="Multi-core processor">Multi-core</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>

<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Cache_(computing)" title="Cache (computing)">Cache</a>

<ul><li><a href="CPU_cache" title="CPU cache">CPU cache</a></li>

<li><a href="Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li>

<li><a href="Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li>

<li><a href="Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li>

<li><a href="Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li>

<li><a href="Cache_coherence" title="Cache coherence">coherence</a></li></ul></li>

<li><a href="Clock_rate" title="Clock rate">Clock rate</a></li>

<li><a href="Clock_signal" title="Clock signal">Clock signal</a></li>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Execution_unit" title="Execution unit">Functional<br>units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li>

<li><a href="Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li>

<li><a href="Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li>

<li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU)

<ul><li><a href="Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li>

<li><a href="Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li>

<li><a href="Branch_predictor" title="Branch predictor">Branch predictor</a></li>

<li><a href="Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li>

<li><a href="Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC)

<ul><li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li>

<li><a href="Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Combinational_logic" title="Combinational logic">Combinational</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a>

<ul><li><a href="Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li>

<li><a href="Gate_array" title="Gate array">Array</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Processor_register" title="Processor register">Processor register</a></li>

<li><a href="Status_register" title="Status register">Status register</a></li>

<li><a href="Stack_register" title="Stack register">Stack register</a></li>

<li><a href="Register_file" title="Register file">Register file</a></li>

<li><a href="Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li>

<li><a href="Memory_address_register" title="Memory address register">Memory address register</a></li>

</ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li>

<li><a href="Instruction_unit" title="Instruction unit">Instruction unit</a></li>

<li><a href="Data_buffer" title="Data buffer">Data buffer</a></li>

<li><a href="Write_buffer" title="Write buffer">Write buffer</a></li>

<li><a href="Microcode" title="Microcode">Microcode</a> <a href="ROM_image" title="ROM image">ROM</a></li>

<li><a href="Counter_(digital)" title="Counter (digital)">Counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Multiplexer" title="Multiplexer">Multiplexer</a></li>

<li><a href="Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li>

<li><a href="Adder_(electronics)" title="Adder (electronics)">Adder</a></li>

<li><a href="Binary_multiplier" title="Binary multiplier">Multiplier</a>

<li><a href="Binary_decoder" title="Binary decoder">Binary decoder</a>

<ul><li><a href="Address_decoder" title="Address decoder">Address decoder</a></li>

<li><a href="Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li>

<li><a href="Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li>

<li><a href="Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean</a></li>

<li><a href="Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li>

<li><a href="Analogue_electronics" title="Analogue electronics">Analog</a></li>

<li><a href="Quantum_circuit" title="Quantum circuit">Quantum</a></li>

<li><a href="Switch#Electronic_switches" title="Switch">Switch</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Power_management" title="Power management">Power<br>management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li>

<li><a href="Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li>

<li><a href="Clock_gating" title="Clock gating">Clock gating</a></li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li>

<li><a href="Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li>

<li><a href="Processor_design" title="Processor design">Processor design</a></li>

<li><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></li>

<li><a href="Hardware_security_module" title="Hardware security module">Hardware security module</a></li>

<li><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li>

<li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>

<li><a href="Pin_grid_array" title="Pin grid array">Pin grid array</a></li>

<li><a href="Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul>

</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-06-21" href="https://en.wikipedia.org/wiki/?title=Program_counter&oldid=1296741014">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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